A Slow Motion Engine for the Analysis of FPGA-Based Prototypes
نویسندگان
چکیده
for the Analysis of FPGA-Based Prototypes Nikolaj Janzen and Franz Josef Rammig Universit at-GH Paderborn, Germany Email: janzen, [email protected] Abstract. Logic emulation based on FPGAs became one of the major techniques of rapid prototyping. Such emulators allow a precise representation of the system`s behaviour but unfortunately the timing can not be mapped precisely. This paper presents an approach to include a slow motion functionality into a FPGA-based emulation, that allows the emulator to re ect precisely the timing of the nal system.
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